The present invention relates to data processing systems and, more particularly, to systems within a central processing unit of the data processing system capable of performing BCD arithmetic operations and conversions to and from binary.
Typically, the data path portion of a central processing unit (CPU) of a data processing system has a configuration as shown in FIG. 1. The arrows in this figure illustrate the flow of data with the broad arrow indicating a set of data in the form of signals representing "1"'s and "0"'s moving through the data path simultaneously and the narrow arrows indicating the signal path of a single datum. The heart of the CPU data path portion is an ALU (arithmetic logic unit) 11, which performs the various arithmetic and logic operations upon operands which are fed into the ALU as input signals. FIG. 1 shows the source of these operand signals to be a register file 10 which sends the operands A and B indicated by the arrows 20 and 21 into the ALU 11. The result of the ALU operation is placed upon the data path 22.
A shifter 12 receives these data signals and can shift these signals "up" or "down" depending upon the operation required of the CPU. For a shift "up" each of the signals of a data set from the ALU is shifted into the next more significant place. A shift "down", on the other hand, shifts each of the data signals into the next less significant place. The data, which, in being shifted up, are shifted into the the shifter 12, are transferred into a shift register 14 one datum or bit at a time. Similarly, if the shifter 12 shifts down, the information shifted out also passes to the shift register 14 one bit at a time. The shift register 14 can also shift data back into the shifter 12. The paths along which the data is shifted between the shifter 12 and the shift register 14 are indicated by the bidirectional arrows 30, 30A, 30B and 30C. These paths vary in accordance with the operation the CPU is required to perform. For conversions of operands in binary format to BCD format or from BCD to binary, the path 30 is used.
The contents of the shift register 14 may be accessed as output signals as indicated by the bidirectional arrows 28, 29 or reentered into the shift register 14 for another operation by the data path 25. Information from the shifter 12 may be accessed immediately as output signals along the path 23 and 29. Alternatively, the results of the ALU 11 and the shifter 12 operations may be sent along the paths 23, 24 back into the register file 10. In this manner, operations, such as division and multiplication, requiring iterative operations by the ALU 11 and the shifting units 12, 14, may be performed. The final result appears at the end of these multiple operation as output signals on the path 29.
The data path 29 is bidirectional so that data outside of the system may be fed into the system. One such example is the transfer of data from memory (not shown) to the CPU along the data paths 29, 24 to be stored into the register file 10 for processing by ALU 11.
Not shown here is a control unit which comprises the other major portion of the CPU which handles the control functions for each of the elements of the data path in the CPU and their timing so that the operation and transmission of data between these elements proceeds in an orderly manner. Such designs and techniques are well known.
However, most operations in these data processing systems are performed in binary format. In certain systems, such as those having CRT display intensive operations, a BCD (binary coded decimal) format is desirable. Software is sometimes used to achieve BCD format results, though the system continues to operate in binary. To avoid the relative lack of speed in a software implementation, hardware alternatives have also been used.
The present invention is a significant advance over the prior art in which, by a novel design in the subsystems of the CPU of a data precessing system, arithmetic operations in BCD format are accelerated and time intervals for converting an operand in binary to BCD and to binary from BCD are minimized. This design of the CPU is attained without disturbing the design of the original circuitry so that the features of the prior-designed subsystems operating a binary are retained. Thus, the present invention permits the CPU to offer results to the user of the system in binary or BCD, as desired.